Page contenant les informations sur la GDCC:
1 – GDCC-DIF Registers
the format is done via the following packet
address = 2 bytes
data = 4 bytes
Adress is 16 bits, data is 32 bits.
Currently the registers are 16 bits.
this is to allow future expansion
Lower bits of data are used first, so a register that returns < 32 bits will return in the lower bits of data space, this is the same for the writes.
When performing a read, the packet must still include the space for the data, even though it will be over written by the GDCC internal processing.
The advantage is the things are symmetric for both reads and writes.
Block 0x1
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Reg 0 + 2
Name: TX/RX Enable
Access from PC: R/W
Description: Bitmap, 1 bit for each DIF channel, set to 1 to enable it in TX (Reg0) + RX (Reg 2) direction.
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Reg 4
Name: Link RTT
Access from PC: R/W (W on link restart only)
Description: Bitmap, 1 bit for each DIF channel.
Set the bits to 1 to prepare to measure RTT on the selected channels. Setting from 0 to 1 is taken into account at next restart link. To end RTT operation, set it to 0 any time.
The RTT is taking the link delay module into account (DCC firmware >= r1425): this means that changing values in the Link Delay registers should impact the RTT measures (also note that changing these delays while in RTT measurement will cause a transient restart of the RTT measurement because the serializer [parallel to RTT, but impacting it] loses RX sync during a few cycles). When all the RTT of all the connected lines are the same, then chances are that the links are synchronized (modulo 1 period on the link).
Link status registers (0xa + 0xb) affected.
To start a RTT measure session:
Write Link RTT register bitmap with bits set = channels to measure
Write Link Restart register bitmap with bits set = channels to measure. This will start a new RTT measure session
The Link status registers should oscillate between 0b010 and 0b011
Wait for the LINK_RTT_DONE of the channels you want to measure to be set to 1. This signals that at least one measure has been performed on the corresponding channel, such that the corresponding LINK_RTTx value is valid
Do nothing or periodically check the LINK_RTTx values of the channel whose LINK_RTT_DONE is 1: this is refreshed continuously while the RTT session is running. Do some stats with these sampled values, etc.
To stop a RTT session:
Clear the Link RTT register bits you want to stop to measure
The Link status registers should be back to 0b101
The Link Done bit for the cleared channels should be clear
The LINK_RTTx values should reflect the last sampled RTT value for the channels that have been stopped
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Reg 6
Name: Link Autoneg Pause
Access from PC: R/W (W 1 on link restart only)
Description: Bitmap, 1 bit for each DIF channel, set to 1 to switch off the selected channels. Setting it from 0 to 1 is taken into account at next restart link. To resume normal operation, set it to 0 any time.
Link status registers (0xa + 0xb) affected.
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Reg 8
Name: Link Restart
Access from PC: W (R should always return 0)
Description: Bitmap, 1 bit for each DIF channel, to restart the link negotiation FSM (lda_protocol_sm.vhd) for the given channels. Will take Regs 4 and 6 into account: Reg 4 first when set, Reg 6 otherwise
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Reg 0xa + 0xb
Name: Link Status
Access from PC: R
Description: Array of 3 bits blocks, 1 block per channel (1st block = lsb of Reg 0xa). Possible values:
« 000 » = starting up
« 001 » = sending_idle_stream
« 010 » = sending loopback command. Waiting for loopback to ack.
« 011 » = sending random data. Shows Remote is looped.
« 100 » = sending link start.
« 101 » = Link is up
« 111 » = Has all gone wrong.
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Reg 0xe
Name: Ling No Signal
Access: R
Description: Bitmap, 1 bit for each DIF channel. Set to 1 when the DIF didn’t do any transition to the DCC for at least 512 clock periods. Could be because the link is not electrically valid, or the DIF didn’t send any 8b/10b idle/k/d transitions for at least 512 clocks.
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Reg 0x10 + 0x11 + 0x12 + 0x13
Name: Link Delay 1..4
Access from PC: R/W
Description: Array of 5 bits blocks, 1 block per channel (1st block = lsb of Reg 0x18). Each value = delay (in number of link periods) to add at TX level. Use this to compensate for non-uniform RTT measurements from DIF channel to channel (see RTT register above).
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Reg 0x18 + 0x19 + 0x1a + 0x1b
Name: Link RTT 1..4
Access from PC: R
Description: Array of 5 bits blocks, 1 block per channel (1st block = lsb of Reg 0x18). Each value = RTT measured, valid during a RTT measurement session when corresponding RTT Link Done is set, and valid after an RTT measurement session. Each value = delay (in number of link periods) measured to transfer data to DIF and back, taking into account the delay added by the link delay register above.
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Reg 0x20
Name: RTT Done
Access: R
Description: Bitmap, 1 bit for each DIF channel. During a RTT measurement session: set to 1 when at least 1 RTT measure has been performed on the corresponding channel (and measure stored in the RTT_LINKx register). Otherwise should be 0.
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Reg 0x22
Name: GET_LNKS_LOCKED
Access: R
Description: Bitmap, 1 bit for each DIF channel, set to 1 when the corresponding DIF channel is known to be connected and locked
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Reg 0x24
Name: Link DCM
Access: R/W
Description: R access = should always be 1, but in effect bit 0 means « DCM locked ». W access = bit 1 (not 0 !) to force the DCM to relock itself (auto-clearing), bit 2 to restart the word clock counter from fresh (auto-clearing, but meaning not fully understood).
2 – GDCC internal registers
This block contain all registers for the GDCC only.
The block is the block 4.(0x4)
Currently, it based on 17 address.
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Reg 0x000
Name : LDA/GDCC enables
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Reg 0x001
Name : LDA/GDCC tx_mux_count
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Reg 0x002
Name : LDA/GDCC reg_pktdelay
Access : R/W
property : expert only
The data is on 16 bits, only 6 lsb bit are used. It corresponds at the delay between each packets at the output of round robin function. The configuration must be:
– 000000 : no delay
– 000001 : 20 ns
– 000010 : 200 ns
– 000100 : 2µs
– 001000 : 20 µs
– 010000 : 200 µs
– 100000 : 2 ms
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Reg 0x006
Name : LDA/GDCC dif_data_mac_l
access : R/W
This is the LSB octet of the PC Mac adress (0–15)
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Reg 0x007
Name : LDA/GDCC dif_data_mac_m
access : R/W
This is the medium octet of the PC Mac adress (16–31)
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Reg 0x008
Name : LDA/GDCC dif_data_mac_h
access : R/W
This is the MSB octet of the PC Mac adress (32–47)
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Reg 0x00e
Name : LDA/GDCC revision
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Reg 0x00f
Name : LDA/GDCC version
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Reg 0x010
Name : LDA/GDCC pktgen_control
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Reg 0x011
Name : LDA/GDCC pktgen_size
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Reg 0x012
Name : LDA/GDCC pktgen_count
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Reg 0x013
Name : LDA/GDCC pktgen_delay
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Reg 0x014
Name : LDA/GDCC pktgen_seed
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Reg 0x015
Name : LDA/GDCC pktgen_txcount
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Reg 0x016
Name : LDA/GDCC pktgen_mac_l
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Reg 0x017
Name : LDA/GDCC pktgen_mac_m
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Reg 0x018
Name : LDA/GDCC pktgen_mach