

                    Core Name: Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII
                    Version: 9.1
                    Release Date: March 24, 2008


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This document contains the following sections:

1. Introduction
2. New Features
3. Resolved Issues
4. Known Issues
5. Technical Support
6. Other Information
7. Core Release History

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1. INTRODUCTION

For the most recent updates to the IP installation instructions for this core,
please go to:

   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm


For system requirements:

   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm



This file contains release notes for the Xilinx LogiCORE
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 solution. For the latest core updates,
see the product page at:

   www.xilinx.com/products/ipcenter/DO-DI-GMIITO1GBSXPCS.htm


2. NEW FEATURES

   - ISE 10.1i software support
   - Virtex-5 FXT support
   - VCS simulator support for Verilog (Linux only)
   - Updated Virtex-5 GTP parameters : PMA_RX_CFG values changed to exclude
     2nd order loop filter
   - Updated Virtex-4 GT11 reset/initialization state machines to match the
     latest recommendations


3. RESOLVED ISSUES

   - ISE Project Navigator GUI : Core Generation Failure
      - version fixed: v9.1
      - CR 453910: the core would fail to generate when using the SGMII standard
        with the TBI from within the ISE Project Navigator GUI.  The core would
        successfully generate when CORE Generator was run as a standalone tool.
        This has now been resolved.


4. KNOWN ISSUES

   The most recent information, including known issues, workarounds, and
   resolutions for this version is provided in the release notes Answer Record
   for the ISE 10.1i IP Update at

   http://www.xilinx.com/support/answers/29767.htm


5. TECHNICAL SUPPORT

   To obtain technical support, create a WebCase at www.xilinx.com/support.
   Questions are routed to a team with expertise using this product.

   Xilinx provides technical support for use of this product when used
   according to the guidelines described in the core documentation, and
   cannot guarantee timing, functionality, or support of this product for
   designs that do not follow specified guidelines.


6. OTHER INFORMATION

   Virtex-5 LXT ES silicon requires transmit signals between the fabric and
   the GTP to be registered and locked down to meet timing. Please refer to
   answer record 24168 and the product User Guide for details on how to do this.


7. CORE RELEASE HISTORY

Date        By            Version      Description
================================================================================
03/2008  Xilinx, Inc.  9.1        Release for ISE 10.1i
08/2007  Xilinx, Inc.  9.0        Release for 9.2i
04/2007  Xilinx, Inc.  8.1 Rev 1  Spartan-3A DSP support
02/2007  Xilinx, Inc.  8.1        Release for ISE 9.1i
10/2006  Xilinx, Inc.  8.0        Release for Virtex-5 and Spartan-3A
07/2006  Xilinx, Inc.  7.1        Release for ISE 8.2i
05/2006  Xilinx, Inc.  7.0 Rev 1  Virtex-4 FX CES4 update
01/2006  Xilinx, Inc.  7.0        Release for ISE 8.1i
06/2005  Xilinx, Inc.  6.0 patch1 Patch release
04/2005  Xilinx, Inc.  6.0        Release for ISE 7.1i
09/2004  Xilinx, Inc.  5.0        Release for ISE 6.3i
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